U.S. Pat. No. 4,935,647 (issued Jun. 19, 1990) is directed to a GaAs device having a current-injecting circuit that generates an initial pulse of capacitor-charging current during a "0"-to "1" output transition. The pulse is sufficiently large to quickly charge the parasitic capacitances, and is of sufficiently brief duration so that the minimum line width of the interconnect metal is substantially equal to that which would be applicable in the absence of the current-injecting circuit. The circuit is described as useful as an available macro for a GaAs array.
FIG. 1 herein schematically illustrates an embodiment of the above-described circuit which is illustrated and described in U.S. Pat. No. 4,935,647. U.S. Pat. No. 4,935,647 is assigned to the assignee of this invention, and the content of that patent is hereby incorporated by reference. The circuit comprises an inverter 10 which includes an enhancement mode (E-mode) pull-down FET 1 having its source "s" coupled to a power bus (V.sub.SS), and its drain "d" coupled to the other power bus V.sub.DD through a pull-up resistive element in the form of a second FET 2. The output of the inverter is the drain "d" of the FET 1, while the input to the inverter is applied to the gate "g" of the FET 1. The resistive element is conveniently a depletion mode (D-mode) FET having its drain "d" tied to the power bus "V.sub.DD ", and its source "S" and gate "g" tied to the drain "d" of the E-mode FET 1. The respective width-to-length ratio of the channel of each FET is indicated in FIG. 1 by the nomenclature "W/L", where W and L are the numerical values of the ratio.
The output of the inverter is coupled to a push-pull buffer comprising a pull-down E-mode FET 4 in series with a resistive device in the form of a D-mode FET 3. The gate of the pull-up D-mode FET 3 is coupled to the drain of the inverter's pull-down FET 1 at an internal node 6. The output of the buffered inverter V.sub.o is the drain of the buffer's pull-down FET 4.
A clamp 8 responsive to the output V.sub.o of the buffered inverter selectively couples the internal node 6 to the power bus V.sub.SS to shunt pull-up drain-to-source current from the inverter's pull-up FET 2 to the bottom rail V.sub.SS. The clamp shunts the current in this manner except for substantially all of the transition period when the output V.sub.o is changing from logic "0" to logic "1".
The clamp 8 comprises an E-mode FET 5 whose drain-to-source path is series-coupled with a diode D1 between the internal node 6 and the power bus V.sub.SS The gate of FET 5 is coupled to the buffer output V.sub.o. The diode may conveniently be the Schottky diode of a FET on the chip.
As a change from "1" to "0" occurs at the input gate of the pull-down FET 1, the voltage at the internal node 6 rises faster than the voltage of the buffer's output V.sub.o, heavily biasing the buffer's D-mode FET 3, and reducing the rise time of the buffer's output V.sub.o. As the buffer's output V.sub.o approaches a logic level "a", the FET 5 of the clamp 8 begins to conduct, returning the internal node to a voltage level approximately equal to a diode drop (0.7 volts) above the power bus V.sub.SS.
In practice, particularly in VLSI chip design, the various interconnect metal lines present on the chip can be long enough to exhibit an electrical resistance sufficient to affect the operation of the chip's components. For example, the power bus voltage may vary slightly between gates relatively near the power input to the chip and macros relatively remote from the power input, resulting in excessive current flow through the gate-to-source Schottky barrier diode of the E-mode FET 5. Such excessive current flows can exceed the electromigration current limits of the chip.
Similarly, a relatively long interconnect between a driver and a driven gate can result in excessive currents in the driver and/or degradation in the biasing of the driven element. By way of illustration, the reader's attention is directed to FIG. 2, which schematically illustrates the circuit of FIG. 1 with the addition of a schematically represented load. In FIG. 2, the capacitor C represents the total load capacitance, which comprises the capacitance of the driven devices (represented here by FET 9) and the capacitance of the interconnect metalization. The diode D.sub.2 represents the gate-to-source Schottky barrier diode of the driven device FET 9. The resistor R represents the resistance of the metal interconnect line. V.sub.n represents the offset in V.sub.ss of the driven device FET 9 due to the IR drops on the V.sub.ss line. The diode D.sub.3 represents the gate-to-source Schottky diode of FET 5.
It can be appreciated from FIG. 2 that the biasing of the driven device FET 9 is degraded if the interconnect line is of such length that resistor R has a significant value, or if the polarity of V.sub.n is such that the gate-to-source voltage of the driven device FET 9 is reduced. This happens because the output voltage of the buffer V.sub.o is clamped by diode D.sub.3 and the voltage drop across R, or V.sub.n, reduces the voltage to the gate of the driven device FET 9.
Moreover, the presence of the resistance R can cause a large amount of current to flow through the gate and source of FET 5, exceeding the electromigration current limits, if FET 3 and FET 4 are sized to provide a large transient current to the load capacitor C.